The present invention relates to microprocessors, and more particularly to the manufacturing of chip scale packages.
Chip scale packages of microprocessors are sensitive to electrostatic discharges. How well they are protected from electrostatic discharges is an important concern. xe2x80x9cChip scale packagesxe2x80x9d, as used in this application, refers to packages in which the carrier on which the chip sits is approximately the same size as the chip. FIG. 1 illustrates a cross-section of a chip scale package manufactured with a conventional method Tessara BGA(copyright). The package 100 includes a chip 110 with a die 120. The die 120 is conventionally composed of a silicon material. The die 120 has a front side 10 and a back side 20. The circuitry (not shown) of the chip 110 is located on the face of the front side 10. The package 100 also includes a carrier (tape) 130 with an array of balls 140 connected to the front side 10 of the chip 110. The balls 140 are soldered to a carrier, in this example a printed circuit board (PCB). The array of balls 140 facilitates the connections between the circuitry on the die 120 and the substrate 150. To facilitate the connections between the die 120 and the balls 140, wires or tabs 160 are connected therebetween via bondingpads 170.
FIG. 2 is a flow chart illustrating a conventional method of manufacturing a chip scale package. Referring to FIGS. 1 and 2 together, first, the conventional wafer fabrication process is performed, via step 202. The wafer is manufactured with a Silicon die 120. The back side 20 of the die 120 is mounted on a tacky plastic tape, via step 204. Using a thin diamond saw, columns and rows of cells are sawed from the front side 10 of the die 120 completely through the Si and into the tacky plastic, via step 206. Then, a carrier tape with chip components (balls and a fan-in pattern of connections between the balls and the chip) such as the one developed by Tessara, Inc., are placed on the front side of the die 120, via step 208. The tape manufactured by Tessara is well known in the art and will not be further described here. A bonding tool is used to bond the wires or tabs 160 to the bonding pads 170, via step 210. With a needle-like tool, viable portions of the die 120 with carrier tape are ejected from the tacky plastic, via step 212. This leaves non-viable portions of the die 120 attached to the tacky plastic. Good dice and bonded carrier tape are place in tray, via step 214, retaining viable portions of the die 120 on the chip 110 while leaving non-viable portions on the tacky plastic. The tape and the non-viable portions of the die 120 are then thrown away. Data may be marked on the back side 20 of the die 120, via step 216. The data may include information such as the lot number, part number, and the speed of the chip 110. The resulting chip 110 has viable die with carrier, balls, and other components attached, as shown in FIG. 1. This chip 110 is then mounted onto a printed circuit board 150, via step 218, to form the final chip scale package 100.
A problem with the conventional method of manufacturing a chip scale packaging 100 related to the fact that the back side 20 of the die 120 is exposed to many environmental 20 factors. The exposed die renders the chip 110 particularly sensitive to possible electrostatic discharge (ESD). ESD can damage the chip 110 in two ways. First, the exposed die 120 can come in contact with a charged object which discharges to the chip 110. This is commonly referred to as the human body model (HBM). Second, the exposed die 120 may come in close proximity to a highly charged body, which induces a charge in the chip 110. This is commonly referred to as the charge device model (CDM). In both models, a high current occurs in the chip 10 for a short period of time, which damages one or more active areas of the chip 110. Thus, the package 100 manufactured with the conventional method is thus particularly sensitive to ESD.
Another problem with the conventional method of manufacturing a chip scale package 100 involves the marking of the package 100 on the back side 20 of the die 120. Infrared (IR) Lasers are often used to write this data directly into the die 120. However, the laser IR travels through the silicon die 120 since silicon is transparent to infrared light (not true of green light). When the light reaches the balls 140 on the front side 10 of the die 120, which are typically composed of Aluminum or some other metal, the light""s energy are deposited on the balls 140 since metals are not transparent to infrared light. This energy causes local melting of the Aluminum metal patterns of the balls 140, damaging the chip 110.
Accordingly, there exists a need for a method of manufacturing a chip scale package which will provide protection against electrostatic discharge and allow the writing of data using an infrared laser onto the chip in the package without causing damage. The present invention addresses such a need.
The present invention is a method for providing chip scale package. The method of the present invention includes providing a die with a first side, a second side, and a plurality of edges; applying a substance which protects against electrostatic discharge to the first side of the die and to the plurality of edges; and providing components on the second side of the die. The method of the present invention protects the chip scale package from electrostatic discharges. High contrast, colored markings may also be placed on the substance without damaging the chip in the package.